The present invention relates generally to the field of power amplifiers in multi-band communication systems. More particularly, the present invention relates to circuitry associated with such power amplifiers, such as harmonic filters, impedance load switching circuits, pre-distortion phase filters, and the like.
In the United States, cellular operating licenses have been awarded by the Federal Communication Commission (FCC) pursuant to a licensing scheme which divides the country into geographic service markets. Cellular licenses were originally granted for radio frequency (RF) blocks in the 800 MHz range. Most 800 MHz cellular telephone systems in the United States utilize the Advanced Mobile Phone Service (AMPS) analog air interface standard. A later generation air interface standard for the 800 MHz band, known as D-AMPS, has subsequently been developed and implemented. The D-AMPS standard comprises both digital and analog cellular communication. Thus, there are presently both analog (AMPS) and digital (D-AMPS) cellular telephone networks in operation at 800 MHz in the United States.
In response to increased demand for cellular services, a number of digital air interface standards were developed for providing efficient digital communication of voice, data, fax and text messages under the umbrella of xe2x80x9cpersonal communications servicesxe2x80x9d or PCS. Operational PCS systems, such as systems based on the GSM TDMA (Time Division Multiple Access) or IS-95 CDMA (Code Division Multiplex Access) air interface standards, are being implemented in the United States in the 1900 MHz frequency range. Meanwhile, existing 800 MHz cellular systems continue to operate. Thus, there are presently operating in the United States analog and digital cellular systems at 800 MHz and digital PCS systems at 1900 MHz. Mobile subscribers who desire to receive services from systems operating at 800 MHz and from systems operating at 1900 MHz must either use two different mobile transceivers or use a single xe2x80x9cdual-bandxe2x80x9d mobile transceiver which can receive and transmit radio frequency (RF) signals in both frequency bands.
Power control is essential to the smooth operation of CDMA communication systems. Since there are many users sharing the frequency spectrum, in order to resolve the near-far multiple-access in a spread-spectrum system, output power for each individual user needs to be adjusted dynamically to maximize the system capacity. For this reason, a typical CDMA handset is operated under a varied output condition. According to actual statistics obtained from the field, a CDMA cellular phone handset spent approximately 95% of its time transmitting output power in a range of 10-30 dB lower than its maximum rated output power. Recognizing this fact, most CDMA handset power amplifiers have lower power (LP) and high power (HP) modes of operation. The purpose of this two-mode operation is to improve the efficiency performance at the LP mode.
FIG. 1 shows a diagram of a typical wireless voice communication device 100, such as a mobile phone handset 100 for cellular telephone use. For the voice interface, device 100 includes a microphone 102 for converting audio signals to electrical signals which the transmitter 104 can then send. Device 100 also includes a receiver 112 connected to a speaker 114. The transmitter 104 and the receiver 112 normally share an antenna 110, although separate antennas may instead be provided.
The transmitter 104 includes, inter alia, a speech coder 120 for encoding the electrical voice signals and forwards them to a modulator 122. Depending on the power mode and network used, the modulator 122 mixes the coded signals to the appropriate frequency band. For example, modulator 122 shifts the signal to approximately 800 MHz in the case of CDMA or 1900 MHz in the case of Wideband CDMA (WCDMA). Power amplifier/load switch 124 amplifies and impedance matches the signal. The load switch portion of the power amplifier/load switch 124 matches the outgoing signal to the required impedance and may also filter out various signal harmonics. Matching impedances helps an amplifier maximize power efficiency and filtering harmonics reduces interference. An isolator 106 and a receive/transmit duplexer 108 connect the power amplifier/load switch circuit 124 and antenna 110. Using this series of components the handset 100 may transmit RF signals using the antenna 110.
The receiver 112 obtains a received RF signal from the antenna 110 via the duplexer 108. An RF receiver 130 prepares the received RF signal for demodulation. A demodulator 132 demodulates the received RF signal to output a demodulated signal, and a speech decoder 134 decodes the demodulated signal to form an audio signal for reproduction on speaker 114.
Considerable power in a wireless communication device is dissipated in the power amplifier (PA) (e.g., power amplifier/load switch 124) and the efficiency of a power amplifier is predominately determined by its output load design. There are two main factors affecting the output load design: 1. class of operation (e.g., class -A, -A/B, -B, -C, -E, etc.); and 2. load impedance at the fundamental and harmonic frequencies. In a typical PA design, the load is designed to achieve the best efficiency performance at its highest output power. For those power amplifiers that need to have low signal distortion (such as CDMA PA), there are the additional linearity requirements that need to be satisfied.
Wireless communication devices typically transmit RF signals at a plurality of power levels. However, the efficiency of the PA significantly varies over the output power range. Because current drain efficiency of the PA is most affected at a higher output power, the PA is designed to maximize efficiency at higher output power levels. One technique to improve power efficiency requires switching the quiescent current of the PA in response to a PA output high power (HP)/low power (LP) mode control change. At the HP mode, the PA is biased with high quiescent current in order to maximize its output current swing; at the LP mode, the PA is biased with low quiescent current in order to reduce current consumption. Another circuit technique that could be considered to improve the efficiency for varied output power system is by load switchingxe2x80x94i.e., the output load is adjusted in accordance to the output power requirements.
Operational efficiency of a power amplifier is dependent on load impedance. A PA is generally designed for maximum output power operation. This usually means the output device xe2x80x9cseesxe2x80x9d a low impedance load. This is necessary to maximize the device""s current swing. However, this low impedance unavoidably leads to a degraded efficiency when the output power level is lowered. In order to achieve improved efficiency performance at lower output power, the output device needs to xe2x80x9cseexe2x80x9d a high impedance load. A switched load circuit is a circuit implementation which provides a two-state (or multi-state) load designxe2x80x94i.e., a low impedance state for high power operation and a high impedance state for low power operation. Hence, the load is adjusted via a xe2x80x9cswitchingxe2x80x9d operation.
The trend of cellular wireless communication is moving toward a multi-mode handset. To simplify the implementation of a multi-mode handset, it is desirable to have components that can operate in multiple frequency bands. This is usually not too difficult a task for many RF components; however, a multi-mode PA is hard to realize because of the narrow band nature of the PA and to its low output load impedance. One method to overcome this problem is to use a switched load technique that can switch the load to the designated impedance in accordance with the selected frequency band.
U.S. Pat. No. 5,774,017 (issued to Adar) (henceforth referred to as the ""017 patent), teaches a multiple-band amplifier. More particularly, it discloses a GaAs MMIC dual-band amplifier for wireless communications for operation at either the 800 MHz or the 1900 MHz band and it provides desired gain and input and output impedance. Switching impedance networks are used at the input and output of the amplifier to provide matching input impedance and desired output impedance for operation in the two bands. Switching impedance networks are also used between any successive stages of the amplifier to provide proper interstage impedance. The dual band amplifier includes a bias control circuit which biases the amplifier to operate in A, B, AB, or C mode. The amplifier can be used for the AMPS 800 or the GSM 900 operation or any other cellular operation such as the PCS 1900 and it can be switched between the two operations by simply applying a proper control signal to the amplifier.
U.S. Pat. No. 6,188,877 (issued to Boesch et al.) (henceforth referred to as the ""877 patent) describes a dual-band, dual-mode power amplifier with reduced power loss. More particularly, it discloses a power amplifier circuit having a driver amplifier stage including a low band driver amplifier and a high band driver amplifier. A final amplifier stage includes a linear mode amplifier for amplifying digitally modulated signals and a saturated (nonlinear) mode amplifier for amplifying frequency modulated (analog) signals. A switching network interconnects the driver amplifier stage and the final amplifier stage. Depending on the desired mode of operation, an appropriate driver amplifier can be coupled to an appropriate final amplifier to most effectively and efficiently amplify analog or digital RF signals in either of a plurality of frequency bands. A matching circuit is coupled to the linear mode final amplifier for impedance matching and for separating D-AMPS (800 MHz band) and PCS (1900 MHz band) digital signals. A power impedance matching circuit is coupled to the output of the saturated mode final amplifier. In one embodiment, an isolator is coupled to the output of one or more of the low band or high band outputs of the duplex matching circuit. In the low band analog path, a duplexer is provided ahead of the coupling means for reducing the RF power requirements on the coupling means. The switching network and input filter stage may precede a driver amplifier stage.
U.S. Pat. No. 6,215,359 (issued to Peckham et al.) (henceforth referred to as the ""359 patent) teaches an impedance matching for a dual band power amplifier. It describes using a switched capacitor circuit to accomplish GSM/DCS dual band load impedance switching and harmonic suppression high level. More particularly, the ""359 patent discloses an exciter matching circuit, interstage matching circuit, and harmonic filter matching circuit match impedances at the input to a two-stage PA, between the first stage and the second stage of the PA, and at the output of the PA for more than one frequency band of interest. In a GSM/DCS dual band radiotelephone, the matching circuits provide low return loss at 900 MHz when the dual band transmitter is operating in the GSM mode. The harmonic filter matching circuit also filters out signals at 1800 MHz, 2700 MHz, and high order harmonics. When the dual band transmitter is in DCS mode, however, the matching circuits provide a low return loss at 1800 MHz and filter out signals at 2700 MHz and harmonics of 1800 MHz.
FIG. 2 shows a prior art load circuit 200 that operates in conjunction with a power amplifier 202. The load circuit of FIG. 2 is not unlike that disclosed in U.S. Pat. No. 6,243,566 to Peckham et al. For simplicity, only the circuit 200 is shown in detail, it being understood that more than one type of amplifier may work with circuit 200.
The circuit 200 includes a signal input node N21 which receives the output from the power amplifier 202. A first transmission line TL21 is connected between node N21 and a second node N22 which is internal to the circuit 200. A second transmission line TL22 is connected between the second node N22 and a third node N23. A first capacitor C21 is connected between second node N22 and ground and a second capacitor C22 is connected between third node N23 and an fourth node N24 which may be an input to the next element or circuit, such as an isolator, in the overall device. Capacitor C22 acts as a DC blocking capacitor, allowing RF signals to pass therethrough.
Load circuit 200 represents an output matching circuit whose impedance is determined by the characteristics of the transmission lines and the capacitance of the capacitor C21. If the power amplifier 202 is configured to operate in HP mode, then the value of capacitor C21 is chosen to lower the impedance seen by the power amplifier 202. For LP mode capacitor C21 is chosen so that the power amplifier 202 sees a higher impedance. Since the value of capacitor C21 determines the impedance seen by the power amplifier 202, it indirectly determines the power efficiency of the power amplifier 202. Typically, manufacturers configure the value of capacitor C21 to operate in HP mode so that phone performance may deal with interference more effectively. Although phone performance may be improved in this configuration, the average power efficiency is reduced and thus battery life suffers.
FIG. 3 shows a prior art load switching circuit 300 that operates in conjunction with a power amplifier 302. Again, for simplicity, only the circuit 300 is shown in detail, it being understood that more than one type of amplifier may work with circuit 300.
The circuit 300 includes a signal input node N31 which receives the output from the power amplifier 302. A first transmission line TL31 is connected between node N31 and a second node N32 which is internal to the circuit 300. A second transmission line TL32 is connected between the second node N32 and a third node N33. A first capacitor C31 is connected between second node N32 and a switch SW31 and a second capacitor C32 is connected between third node N33 and switch SW31. The circuit 302 also includes a third capacitor C33 connected between third node N33 and a fourth node N34 which may be an input to the next element or circuit, such as an isolator, in the overall device. Capacitor C33 acts as a DC blocking capacitor, allowing RF signals to pass therethrough.
Switch SW31 is an electronic switch which connects either C31 or C32 to ground at any given instant, depending on a mode input 304. The switch SW31 is typically implemented by a transistor circuit which has two mutually exclusive outputs driven by a mode input 304 from a logic circuit, a processor (not shown), or other such known device. Thus, load switch 300 represents an output matching circuit designed for power efficiency in either the LP or the HP mode, the selected mode being controlled by a mode input signal.
In response to a mode input signal of a first type (e.g., low voltage), capacitor C31 is coupled to ground via switch SW31 and capacitor C32 is unconnected to ground. Transmission lines TL31, TL32 and capacitor C31 operate in conjunction with power amplifier 302 to provide a first predetermined output impedance suitable for 1900 MHz operation.
In response to a mode signal of a second type (e.g., high voltage), capacitor C32 is coupled to ground via switch SW31 and capacitor C31 is unconnected to ground. In such case, the two transmission lines TL31, TL32 and capacitor C32 operate in conjunction with power amplifier 302 to provide a second predetermined output impedance suitable for 800 MHz operation.
The load switching circuit 300 of FIG. 2 is not unlike that disclosed in FIG. 13 of U.S. Pat. No. 5,774,017 to Adar which shows each capacitor C31, C32 connected to a separate switch, the two switches acting in a complementary and mutually exclusive manner.
The present invention is directed to a power amplifier circuit that includes a power amplifier responsive to a power mode signal, the power amplifier having a power amplifier output node, and a power amplifier load circuit that is also responsive to the power mode signal, the power amplifier load circuit having a load circuit input node connected to the power amplifier output node. The power amplifier and the power amplifier load circuit of the present invention may be implemented as a GaAs integrated circuit.
The power amplifier load circuit may include a first transmission line coupled between the load circuit input node and a first node, a second transmission line coupled between the first node and a second node, a harmonic filter coupled between the load circuit input node and a common node, a first capacitor coupled between the first node and the common node, and a first switch coupled between the common node and ground, wherein the first switch is responsive to the power mode signal. In a first embodiment, the power amplifier load circuit also includes a second capacitor and a second switch connected to one another in series, between the second node and ground, wherein the second switch is responsive to a band select signal. In a second embodiment, the power amplifier load circuit also includes a second capacitor coupled between the second node and the common node. In a third embodiment, the power amplifier load circuit also includes a second capacitor coupled between the second node and ground.
Thus, in one aspect, the power amplifier load circuit may include a first transmission line coupled between the load circuit input node and a first node; a second transmission line coupled between the first node and a second node; a harmonic filter coupled between the load circuit input node and a common node; a first capacitor coupled between the first node and the common node; a first switch coupled between the common node and ground; and a second capacitor and a second switch connected to one another in series between the second node and ground; wherein the first switch is responsive to said power mode signal and the second switch is responsive to a band select signal.
In another aspect, the power amplifier load circuit may include a first transmission line coupled between the load circuit input node and a first node; a second transmission line coupled between the first node and a second node; a harmonic filter coupled between the load circuit input node and a common node; a first capacitor coupled between the first node and the common node; and a second capacitor coupled between the second node and the common node; and a first switch coupled between the common node and ground, wherein the first switch is responsive to said power mode signal.
In yet another aspect, the power amplifier load circuit may include a first transmission line coupled between the load circuit input node and a first node; a second transmission line coupled between the first node and a second node; a harmonic filter coupled between the load circuit input node and a common node; a first capacitor coupled between the first node and the common node; a first switch coupled between the common node and ground; and a second capacitor coupled between the second node and ground. wherein the first switch is responsive to said power mode signal.
In yet another aspect, the power amplifier load circuit may include a first transmission line coupled between the load circuit input node and a first node; a second transmission line coupled between the first node and a second node; a harmonic filter and a first switch connected to one another in series, between the load circuit input node and ground; a first capacitor coupled between the first node and a common node; a second capacitor coupled between the second node and the common node; and a second switch coupled between the common node and ground, wherein the first and second switches are responsive to the power mode signal.
In yet another aspect, the power amplifier load circuit may include a first transmission line coupled between the load circuit input node and a first node; a second transmission line coupled between the first node and a second node, a filter and a first switch connected to one another in series, between the load circuit input node and ground; a first capacitor and a second switch connected to one another in series, between the first node and ground; and a second capacitor and a third switch connected to one another in series, between the second node and ground; wherein the first, second and third switches are all responsive to the power mode signal.
The power mode signal may correspond to one of a low power mode signal and a high power mode signal, the low power mode signal may correspond to a low-power mode of the power amplifier, and the high power mode signal may correspond to a high-power mode of the power amplifier. The low power mode signal, which may have a voltage of approximately 0V, may open the first switch, and the high power mode signal, which may have a voltage of approximately 3V, may close the first switch.
In another preferred aspect of the present invention, the harmonic filter may comprise a filter inductor and a filter capacitor. The filter inductor may have an inductance of approximately 0.75 nH and the filter capacitor may have a capacitance of approximately 14 pF. The first transmission line may have an impedance of approximately 75 ohms.
In yet another aspect, the power amplifier circuit of the present invention may further comprise: a fourth transmission line coupled to the amplifier output node; a second inductor coupled between the fourth transmission line and a battery voltage input node; and a fourth capacitor coupled between the battery voltage input node and ground.
The power amplifier of the present invention may include a phase shift circuit coupled to an power amplifier input node, a first amplifier stage coupled to the phase shift circuit, and a second amplifier stage coupled between the first amplifier stage and the power amplifier output node, wherein the phase shift circuit, the first amplifier stage, and the second amplifier stage are responsive to the power mode signal.
In one embodiment, the phase shift circuit may comprise a second capacitor coupled between the power amplifier input node and a first internal node; an inductor coupled between the first internal node and a second internal node; a third capacitor coupled between the second internal node and the first amplifier stage; a first diode coupled between the first internal node and ground; and a second diode coupled between the second internal node and ground, wherein the power mode signal is input to the first internal node.
In another embodiment, the phase shift circuit may comprise a second capacitor coupled between the power amplifier input node and a first internal node; an inductor coupled between the first internal node and a second internal node; a third capacitor coupled between the second internal node and the first amplifier stage; a fourth capacitor coupled between the first internal node and a third internal node; a fifth capacitor coupled between the second internal node and the third internal node; and a third switch coupled between the third internal node and ground, wherein the third switch is responsive to the power mode signal.
The power amplifier""s first amplifier stage may comprise a first transistor having a first transistor base, a first transistor emitter and a first transistor collector; and a first current mirror circuit configured to stabilize a voltage at the first transistor base, while the second amplifier stage may comprise a second transistor having a second transistor base, a second transistor emitter and a second transistor collector; and a second current mirror circuit configured to stabilize a voltage at the second transistor base, wherein the first and second current mirror circuits are responsive to the power mode signal.
The power amplifier""s first amplifier stage may further comprise a first input match circuit coupled between the phase shift circuit and the first transistor base; a first output match circuit coupled between the first transistor collector and the second amplifier stage; and an inductor and transmission line connected between a first battery voltage input node and the first transistor collector, and a capacitor connected between said first battery voltage input node and ground, while the second amplifier stage may further comprise a second input match circuit coupled between the first output match circuit and the second transistor base; and an inductor and transmission line connected between a second battery voltage input node and the second transistor collector, and a capacitor connected between said second battery voltage input node and ground.